The cellular phone industry continues to thrive by providing support for Bluetooth personal area networking, positioning technology based on GPS and wireless LAN for high-speed local-area data access. Sophisticated applications, such as MP3 audio playback, camera functions, MPEG video and digital TV further entice a new wave of handset replacements. Such application support dictates a high level of memory integration together with large digital signal processing horsepower and information flow management, all requiring sophisticated DSP and microprocessor cores. To keep cost and power dissipation down, as well as to constrain growth of printed circuit board (PCB) real estate, the entire radio, including memory, application processor (AP), digital baseband (DBB) processor, analog baseband and RF circuits would ideally be all integrated onto a single silicon die with a minimal number of external components.
Currently, the DBB and AP designs invariably migrate to the most advanced deep-submicron digital CMOS process available, which usually does not offer any analog extensions and has very limited voltage headroom. Design flow and circuit techniques of contemporary transceivers for multi-GHz cellular applications are typically analog intensive and utilize process technologies that are incompatible with DBB and AP processors. The use of low-voltage deep-submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits. Furthermore, any mask adders for RF/analog circuits are not acceptable from fabrication cost standpoint. Consequently, a strong incentive has arisen to find digital architectural solutions to the RF functions. One approach to reduce the cost, area and power consumption of the complete mobile handset solutions is through integration of the conventional RF functions with the DBB and AP.
Quadrature modulators are in widespread use today. A block diagram illustrating a prior art Cartesian architecture with I and Q baseband signals is shown in FIG. 1. The modulator, generally referenced 10, comprises a coder 12, I and Q TX pulse-shaping filters 14, 16, cos and sin multipliers of a local oscillator clock 18, 20 and adder 22. In operation, the input bit stream bk is converted by the coder to I (real) and Q (imaginary) symbols. These are pulse-shaped and the resulting baseband signals are multiplied by the cos and sin signals of the local oscillator to generate in-phase and quadrature phase components, respectively. These are combined to generate the output RF signal x(t). Note that this Cartesian modulation scheme could be implemented digitally, which is desirable considering the benefits of digital implementation of circuitry which is typically implemented in analog.
Complex modulation may also be generated using a polar modulation scheme to substitute for the quadrature modulation of FIG. 1. A circuit diagram illustrating prior art polar complex modulation based on direct phase and amplitude modulation is shown in FIG. 2. The circuit, generally referenced 30, comprises a coder 32, I and Q TX filters 34, 36, polar coordinate converter 38, local oscillator 40 and multiplier 42.
In operation, the bits bk to be transmitted are input to the coder, which functions to generate I (real) and Q (imaginary) symbols therefrom according to the targeted communications standard. The I and Q symbols are pulse-shaped and the resulting baseband signals are converted to phase (Ang{s(t)}), and magnitude (Mag{s(t)}) baseband signals by the polar coordinate converter 38, typically implemented using what is known as a COordinate Rotation DIgital Computer (CORDIC). This block performs the conversion from Cartesian to polar coordinates of amplitude A=√{square root over (I2+Q2)} and phase
                    φ        =                  arctan          ⁢                                    Q              I                        .                                                          The phase data is used to phase modulate the local oscillator 40 to generate the appropriate constant-envelope frequency modulated signal cos(ωct+φ(t)), which is effectively multiplied in multiplier/mixer 42 by the magnitude data resulting in the output modulated RF signal denoted by x(t)=A(t) cos(ωct+φ(t)) .
Note that this polar modulation scheme is well suited for digital implementation. A problem arises, however, in that the amplitude and phase modulation paths have entirely different modulators and these two paths must be well aligned in their timing. Even slight misalignment could result in intolerable distortion of the output modulated RF signal.
Considering an all-digital implementation, the local oscillator 40 can be made extremely accurate. By nature, the polar architecture natively operates in the frequency domain where the frequency is the derivative of the phase with respect to time. Depending on the type of modulation implemented, the change in frequency Δf from one command cycle to another can be very large for sudden phase reversals that occur near the origin in the I/Q domain representing the complex envelope.
The conventional Cartesian modulator, on the other hand, operates natively in the phase domain and avoids handling the large swings in frequency. A disadvantage of this scheme, however, is in its difficulty to achieve high resolution compared to the polar scheme. Additionally, amplitude and phase mismatches of the I and Q paths result in modulation distortion.
The prior art analog quadrature Cartesian modulator structure has several disadvantages. Analog Cartesian modulators (1) require analog intensive compensation mechanisms to minimize the impact of modulator impairments, such as I/Q gain imbalance and phase orthogonality error, (2) may require a surface acoustic wave (SAW) filter in the transmit path, which adds considerable cost and silicon area, to reduce noise levels of traditional analog circuitry, (3) make adaptation difficult to different radio standards due to the analog nature of the modulator.
Prior art polar architectures also have several disadvantages, including (1) requiring wideband frequency modulation of the all digital phase locked loop (ADPLL), thereby complicating the varactor banks and associated control circuitry required by such architectures, (2) requiring a calibration procedure to determine and normalize the gain of the digitally controlled oscillator (DCO), whose accuracy is crucial and somewhat problematic in wideband modulation, (3) requiring accurate and problematic time-alignment tuning between the amplitude and phase modulating signals, in particular when the amplitude modulation is analog, (4) requiring a high-speed COordinate Rotation DIgital Computer (CORDIC) mechanism used to convert from Cartesian to polar, (5) having wider spectral replicas where the bandwidth of the spectral replicas is equivalent to that of the envelope signal rather than to the narrower bandwidth of the quadrature components I and Q, and (6) limited capability for carrier leakage cancellation.
Thus, there is a need for a modulation scheme that (1) is fully digital, (2) able to generate complex I and Q modulation at RF frequencies, (3) avoids the disadvantages of prior art analog Cartesian and polar modulation schemes, (4) is well suited for implementation in deep submicron CMOS processes, and (5) is able to address any desired modulation scheme including WCDMA and other advanced modulation schemes.